The wireless LAN has been standardized by the IEEE (Institute of Electrical and Electronics Engineers) 802.11 committee. Also, data whitener encoding algorithms are described in IEEE, "Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications", Draft Standard IEEE 802.11, P802.11D3, pp. 179-180, 183-184 and 189, Jan. 25, 1996.
Referring to the drawings FIG. 1 shows a frame format described therein, a transmit frame used in a wireless LAN of frequency hopping spectrum spreading (FH-SS) type and with a transmit speed of 2 Mbps will be explained below.
As shown in FIG. 1, in the transmit frame, a 80-bit preamble 53 including a repetition of "1" and "0" and a following 16-bit start frame delimiter (SFD) 54 are transmitted to show that effective data follow to the receive side. After SFD 54, a 16-bit header 55 which includes information as to the transmit data length and the transmit frame is transmitted and then transmit data 56 actually desired to be transmitted is then transmitted. The transmit data 56 has a variable length.
Here, by whitener encoding, 2-bit stuff bits 52 are inserted at intervals of 64 bits. In order to suppress the DC bias to the transmit frame, the transmit data 56 are transmitted so that data in a 64-bit section are bit-inverted between logical high level "1" and low level "0" to the actual transmit data 56 by the whitener encoding.
In this case, the stuff bit 52 inserted before the 64-bit section to be bit-inverted is preset to be "11". Therefore, when the stuff bit 52 is the received transmit frame is "11", transmit data to follow this are bit-inverted again to receive the correct data by the receive side. CRC 57 for error check is added to the end of the transmit frame.
FIG. 2 is a block diagram showing an example of conventional data processing equipment for wireless LAN that is composed according to the whitener encoding algorithm describe din IEEE 802.11. Its operation will be explained with reference to FIGS. 1 and 2.
Parallel data type transmit data are first input to a parallel-to-serial converter (P to S) 11. The parallel-to-serial converter 11 converts the transmit data into serial data type. The serialized transmit data 56 are then randomized by a scrambler 12.
The scrambled data are then input to a n-bit (64-bit) shift register 13. The 64-bit shift register 13 takes out every 64-bit data from the transmit data 56 in the transmit frame 51. For the 64-bit data taken out, a weight circuit 36 and an adder A 31 add a weight to each bit. This is equal to conduct `(bias next block)=Sum {weight (b(32)}` in the IEEE 802.11 algorithm. Data b(1) to b(32) in this algorithm are 2-bit symbol data taken out by the 64-bit shift register 13, and data b(0) are the stuff bit 52. A 2-bit stuff insertion circuit 14c inserts the stuff bit 52 to every 64 bits in the frame. The initial value of the stuff bit 52 is b(0)=00.
As shown uppermost in a timing chart for explaining the operation in FIG. 3 and a timing chart for the following section in FIG. 4, the weight values are data to be weighted to every 2 bits, are described later, by the weight circuit 36. Here, the waveform of the second row in FIGS. 3 and 4 represents the output of the scrambler 12. For example, `81h` in section B1 represents data of `10000001`, and a weight output corresponding to this data is `+3-3-3-1`. Namely, `+3` is output for 2 bit symbol data, `10`, of the transmit data 56, `+1` for `11`, `-1` for `01` and `-3` for `00'.
According to the above algorithm, for example, weight (b(1))=+3 for b(1)=10, weight (b(2))=-1 for b(2)=-01.
The adder A 31 is reset when starting the frame transmission and after conducting the operation for every 64 bits. By the resetting the content of the adder A 31 is cleared to be `0`.
Here, provided that the calculation result of the adder A 31 is signal `bias` and the accumulated calculation result of an adder B 33 is signal `accum`, a comparator 33 judges whether or not (bias)*(accum)&gt;0. This is equal to conduct `If={[(accum)*(bias next block)&gt;0]}then . . .` in the above-mentioned algorithm.
When the judged result is (bias)*(accum)&gt;0, the comparator 33 outputs `0`, and, when (bias)*(accum)&lt;0, the comparator 33 outputs `1`.
When the comparator 33 outputs `0`, a bit inversion circuit 15 conducts bit inversion to 64-bit data used in the operation of `bias` when each of the 64-bit data is output. This is equal to conduct `Invert{b(0), . . . , b(N)}` in the algorithm. When the comparator 33 outputs `1`, the bit inversion is not conducted.
Also, when the comparator 33 outputs `0`, a sign inversion circuit 34 conducts the inversion of the sign(+/-) of `bias` to be output from the adder A 31. This is equal to conduct `(bias next block)=-(bias next block) ` in the algorithm. When the comparator 33 outputs `1`, the inversion of sign is not conducted.
As described above, the adder A 31 conducts the addition of transmit data to ever 64- bit section, and the adder B 32 conducts the addition of the result obtained by the adder A 31. The result of the adder B 32 is stored in a register 35, and then the values of the adder A 31 and the register 35 are compared by the comparator 33 to every 64-bit section. According to the result of the comparator 33, the sign inversion circuit 34 inverts the code of the result of the adder A 31, and the bit inversion circuit 15 conducts the inversion of each bit, `1,``0`, in the transmit data.
Next, the conventional whitener encoding operation will be explained with reference to FIGS. 2, 3 and 4. FIGS. 3 and 4 show an example of transmit data after scrambling. (E3h, CAh, 9Bh, 87h, BFh, DFh, 3Eh, EFh) (section A1 in FIG. 3), (81h, C3h, 38h, 63h, 2Ah, 39h, 85h, 89h) (section B1 in FIG. 3), and (A4h, B2h, 61h, 2Ah, 4Bh, CCh, 9Ah, 58h) (section C1 in FIGS. 3 and 4), which are hexadecimal data and are sequentially transmitted from each LSB.
For example, when `63h` is transmitted from LSB, `11000110` is sent out. Though data in section A1 are not shown in FIG. 3, they are equal to A2.
The data in section A1 are shifted by 64 bits by the 64 bit shift register 13 and are transmitted to section A2 as transmit data. In like manner, data in section B1 is transmitted to section B2 and data in section C1 are transmitted to section C2. The reason why data are thus shifted by 64 bits is that 64-bit data have to be transmitted after judging whether to conduct bit-inversion or not after calculating a weight according to a weight operation method described later to the 64-bit data.
The adder A 31 conducts the addition of 64-bit data while weighting. The weight is `+3` for data `10`, `+1` for `11`, `-1` for `01` and `-3` for `00`. According to this, for example, when `11000110` is added with the weights, (11)+(00)+(01)+(10)=+1-3-1+3=0 is obtained.
At timing (1) in FIG. 3, calculating the sum of weight values in section A1 by the weight circuit 36 and the adder A 31, +1-3-1+1-1-1-3+1+1-1+3-1+1+3+1-1+1+1-1+1+1+3+1-1+1+1-3+1+1-1+1=+8 is obtained. As to section A1, the result of the adder A 31 is, as it is, stored in the register 35.
At timing (2) in FIG. 3, calculating the sum of weight values in section B1 by the weight circuit 36 and the adder A 31, +3-3-3-1+1-3-3+1+1-1+1-3+1-3-1+3-1-1-1-3+3-1+1-3+3+3+3+3-3-1-1+3-1-3-1=-16 is obtained.
Also, at this timing, the result (=-16) of the adder A 31 and the value (=+8) of the register 35 are compared by the comparator 33. Thereby (bias)*(accum)&lt;0 is obtained, and therefore no signal to invert data is output to the sign inversion circuit 34 and bit inversion circuit 15.
In FIG. 3, the comparator 33 outputs `1`. Namely, the inversion of sign is not conducted, and therefore the sign inversion circuit 34 outputs `-16` and the transmit data in section B2 are transmitted as data in section B1 as it is without bit-inverting. The adder B 32 adds the output (-16) of the sign inversion circuit 34 to the output (+8) of the register 35, thereby (-8) is obtained. The result of the adder B 32 is stored in the register 35.
In like manner, at timing (3) in FIG. 4, calculating the sum of weight values in section B1 by the weight circuit 36 and the adder A 31, -3+3-1-1-1-3+1-1+3-3-1+3-3+3-1-3+1-1-3+3-3+1-1-1+3-1-3-3+3+3=-10 is obtained.
At this timing, the result (=-10) of the adder A 31 and the value (=-8) of the register 35 are compared by the comparator 33. Thereby (bias)*(accum)&gt;0 is obtained, and therefore a signal to invert data is output to the sign inversion circuit 34 and bit inversion circuit 15.
In FIG. 4, the comparator 33 outputs `0`. Namely, the inversion of sign is conducted, and therefore the sign inversion circuit 34 outputs `+10` and the transmit data in section C2 are transmitted by bit-inverting data in section C1. The adder B 32 adds the output (+10) of the sign inversion circuit 34 to the output (-8) of the register 35, thereby (+2) is obtained. The result of the adder B 32 is stored in the register 35.
For the section that transmit data are bit-inverted, the stuff bit is `11`. When the receive side judges that the stuff bit is `11`, it inverts 64-bit data to follow again.
The effect of the whitener encoding for suppressing DC bias is as follows: For example, when data in section C2 are not inverted. the value of the register 35 after completing section C2 is -16=+8 (register value for section B1)-16(output of the sign inversion circuit 34)-10(sum of weight values for section C1). Therefore, the weight value of the transmit data must be biased to (-) side. Here, by bit-inverting data in section C2, the register value becomes (+8-16 +10)=+2. Thus, the weight value is not highly biased, while it is moved to (+) side.
By conducting the above-mentioned data processing, the numbers of `1` and `0` in the transmit data can be adjusted, thereby suppressing the DC bias of the transmit data.
However, the conventional data processing equipment for conducting the whitener encoding must have an increased circuit composition. This is because it is composed of the two adders 31, 32 to conduct the weight operation, the sign inversion circuit 34 to invert the weight operation result, the register 35 to store the past weight operation result and the comparator 33 to judge whether to invert the transmit data or not, other than the shift register 13 and bit stuff circuit 14.